• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An object of the present invention is to reduce the wiring resistance at a low level and to reduce the nonuniformity within the same lot of wiring resistance in a semiconductor device having a multilayer wiring structure wherein at least the lower wiring layer is an aluminum wiring layer. The contact holes 31 and 51 are formed in the interlayer insulating films 3 and 5 of the upper and lower wiring layers 1, 2 and 4 by dry etching. In the method for forming a contact hole of the present invention, this dry etching is performed in two stages. The etching of the first step is performed by supplying CF 4 , CHF 3 , Ar, and N 2 into the etching chamber. The etching of the second step is performed by supplying CF 4 , CHF 3 and Ar into the etching chamber.
    公开号:KR20010041383A
    申请号:KR1020007009508
    申请日:1999-12-28
    公开日:2001-05-15
    发明作者:나가마사 시오까와；아쯔시 야마모또
    申请人:아사히 가세이 마이크로시스템 가부시끼가이샤；
    IPC主号:
    专利说明:

    Method for forming contact hole {Method For Forming Contact Hole}
    In manufacturing a semiconductor device having a multi-layered wiring structure, contact holes are formed in the interlayer insulating film in order to connect the upper and lower wiring layers. A conventional process for forming a contact hole is performed as follows, for example.
    First, a silicon oxide film is formed as an insulating film on the lower aluminum wiring layer. Next, a resist film is formed on this silicon oxide film. The resist pattern is formed by transferring the mask pattern for contact holes to the resist film by photolithography. Subsequently, dry etching of the silicon oxide film is performed through this resist pattern.
    As the etching gas for dry etching, for example, there is used a mixed gas of CF 4 and CHF 3. In addition, in addition to the etching gas, the Ar gas and the N 2 gas are supplied into the chamber during etching for the following purposes. Ar gas is added to dilute the etching gases CF 4 and CHF 3 .
    There are two main purposes of adding nitrogen, one of which is to prevent the withdrawal of the resist (cutting around the contact hole of the resist pattern) during etching. The other is to suppress the formation of a polymer which causes the wiring resistance to increase in the sidewall of the contact hole during etching, and to make it easy to remove with an organic cleaning liquid or the like even when the polymer is formed.
    After forming the contact holes in this manner, the conductors connecting the upper and lower wiring layers are deposited into the contact holes (for example, the formation of a tungsten plug) to form the upper aluminum wiring layer.
    However, the semiconductor device of the multilayer wiring structure obtained in the above-described prior art tends to have high wiring resistance, and at the same time, there is a problem that nonuniformity occurs in wiring resistance within the same lot.
    TECHNICAL FIELD This invention relates to the formation of contact holes performed as a step in the manufacture of semiconductor devices.
    BRIEF DESCRIPTION OF THE DRAWINGS The figure for demonstrating the method of embodiment of this invention. It is sectional drawing which shows the semiconductor device of a multilayer wiring structure.
    Fig. 2 is a graph showing test results for examining wiring resistance of a semiconductor device in which contact holes are formed by a method corresponding to an embodiment of the present invention, and showing a distribution within one lot of voltage measurements.
    FIG. 3 is a diagram showing test results for examining wiring resistance of a semiconductor device in which contact holes are formed in a method corresponding to Comparative Example (Comparative Example 1) of the present invention. FIG. Graph to show.
    FIG. 4 is a diagram showing test results for examining wiring resistance of a semiconductor device in which contact holes are formed by a method corresponding to Comparative Example (Comparative Example 2) of the present invention. FIG. 4 shows a distribution within one lot of voltage measurements. Graph to show.
    SUMMARY OF THE INVENTION The present invention has been made in view of the problems of the prior art, and in a semiconductor device having a multilayer wiring structure wherein at least the lower wiring layer is an aluminum wiring layer, the problem is that the wiring resistance is kept low and the wiring resistance is reduced within the same lot. Shall be.
    <Start of invention>
    In order to solve the above problems, the present invention provides a method for forming a contact hole by forming an insulating film on an aluminum wiring layer and using a predetermined etching gas for this insulating film and dry etching through a resist pattern. And a second etching step of etching without adding nitrogen to the etching gas after the first etching step of adding and etching is performed for a predetermined time.
    In the method of the present invention, it is preferable that the processing time of the first etching step is substantially the same time as the time when the minimum film thickness portion of the insulating film is etched in the thickness direction.
    As an etching gas used by the method of this invention, the gas containing a fluorocarbon system gas is mentioned.
    As an aluminum wiring layer used by the method of this invention, the aluminum alloy layer which consists of an aluminum alloy containing copper (Cu) and / or silicon (Si) is mentioned.
    If the etching performed by adding nitrogen to the etching gas is continued even after the etching depth reaches the aluminum wiring layer surface, AlN is formed on the aluminum wiring layer surface serving as the bottom surface of the contact hole. In contrast, in etching performed without adding nitrogen to the etching gas, it is estimated that such AlN is not formed. And when a contact hole is formed by the etching method which adds nitrogen to an etching gas because this AlN exists, the multilayer wiring structure obtained compared with the case where a contact hole was formed by the etching method which did not add nitrogen to an etching gas. The wiring resistance of the semiconductor device is considered to be high.
    Therefore, in order to make wiring resistance small, it is preferable to form a contact hole by the etching method which does not add nitrogen to etching gas. However, in this etching method, the effect of preventing the retreat of the resist and the suppression effect of polymer formation on the contact hole sidewall cannot be obtained. As a result, contact holes are formed larger than the set value, and at the same time, a problem arises in that wiring resistance is increased under the influence of the polymer.
    In contrast, in the method of the present invention, after the etching (first etching step) for adding nitrogen to the etching gas is performed for a predetermined time, the etching (second etching step) without adding nitrogen to the etching gas is performed. Therefore, until the predetermined time elapses from the start of etching, the above-described action of preventing the resist retreat and the formation of the polymer can be obtained, and after the predetermined time, the above-described action of preventing AlN formation can be obtained.
    Therefore, if the processing time of a 1st etching process is set suitably according to the thickness in the upper part of the aluminum wiring layer of an insulating film, the above-mentioned resist regression and polymer formation can be suppressed small, suppressing AlN formation.
    In particular, when the processing time of the first etching process is substantially the same time as the time when the minimum film thickness portion of the insulating film on the aluminum wiring layer is all etched in the thickness direction, the first etching process is performed at the minimum film thickness portion of the insulating film. Is substantially terminated when the etching depth of the resin reaches the aluminum wiring layer surface. As a result, AlN formation is almost completely prevented.
    As a result, formation of a contact hole larger than a set value is prevented, the wiring resistance of the semiconductor device of the multilayer wiring structure obtained at the same time is suppressed low, and the nonuniformity of wiring resistance in the same lot also reduces.
    <Best form for carrying out invention>
    EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described.
    Here, an example in which the method for forming the contact hole of the present invention is applied when the semiconductor device having the wiring structure shown in FIG. 1 is manufactured will be described. This semiconductor device is a semiconductor device having a multilayer wiring structure having three layers of aluminum wiring layers.
    In this embodiment, the contact hole 31 is formed in the insulating film 3 between the first wiring layer 1 and the second wiring layer 2 of the semiconductor device of FIG. 1, and the second wiring layer 2 and the third wiring layer 3 are formed. In forming the contact hole 51 for the insulating film 5 between the wiring layers 4, dry etching through the resist pattern was performed as follows.
    First, in addition to the CF 4 gas and the CHF 3 gas supplied as the etching gas in the etching chamber as the first etching process, the Ar gas and the N 2 gas are also simultaneously supplied to perform plasma etching. Subsequently, in addition to the CF 4 gas and the CHF 3 gas supplied as the etching gas into the etching chamber as the second etching process, only Ar gas is simultaneously supplied to perform plasma etching.
    About the other processes, a conventionally well-known method can be employ | adopted.
    In fact, a semiconductor device having the wiring structure of FIG. 1 was produced as a TEG (Test Element Group) for measuring wiring resistance. In this semiconductor device, the first wiring layer 1, the second wiring layer 2, the second wiring layer 2 and the third wiring layer 4 are connected by a plurality of tungsten plugs 8, respectively.
    Each of the first to third wiring layers 1, 2, and 4 is formed by dry etching the aluminum alloy film (Si content rate: 1 wt%, Cu content rate: 0.5 wt%) through a resist pattern. The film thickness of the aluminum alloy film was 4000 kPa in the first and second wiring layers 1 and 2 and 7000 kPa in the third wiring layer 4.
    As the insulating films 3 and 5, a silicon oxide film was formed by the CVD method, and the surface thereof was flattened by the CMP method, which is a mechanical planarization method. The film thicknesses of the insulating films 3 and 5 were formed so as to be 10000 to 15000 kPa in the upper portion of the lower wiring layer. As the insulating films 3 and 5, a silicon oxide film may be formed so that the surface becomes flat by using the CVD method and the spin-on glass method together.
    The contact holes 31 and 51 were formed on these insulating films 3 and 5 by performing dry etching through a resist pattern under the following conditions.
    <Etching condition>
    Etching Equipment: Applied Material Japan's Plasma Etching Equipment "P-5000 MxP +"
    Pressure in chamber: 20O mTorr
    High frequency power: 700 W
    Hazard: 30 Gaus
    Temperature at the top of the chamber: 40 ° C
    Lower chamber temperature: 40 ° C
    Helium pressure for cooling: 14 Torr
    Gas supply into the etching chamber:
    Ar; 200 sccm
    CF 4 ; 30 sccm
    CHF 3 ; 30 sccm
    N 2 ; 10 sccm in the first etching process
    0 (not supplied) in the second etching process
    Processing time of the first etching step: 125 seconds (equivalent to the time that the insulating films 3 and 5 are etched 10000 Pa)
    Processing time of the second etching step: 165 seconds (equivalent to the time when the insulating films 3 and 5 are etched at 13000 Pa)
    Thereafter, the resist remaining on the insulating films 3 and 5 was removed by plasma ashing, and then the wafer was washed with an organic cleaning liquid. Next, the titanium film 6 was formed in the film thickness of 300 kPa by the sputtering method in the whole surface of the wafer including the wall surface and the bottom surface of the contact hole 31,51. Thereafter, a titanium nitride film 7 was formed on the titanium film 6 with a film thickness of 1000 GPa.
    On the titanium nitride film 7, a tungsten film was formed at 6000 kPa by the CVD method using WF 6 , H 2, and SiH 4 as the main raw material gases. As a result, tungsten is deposited through the titanium film 6 and the titanium nitride film 7 in the contact holes 31 and 51 and on the insulating films 3 and 5. Then, this tungsten film was etched back by reactive ion etching using SF 6 and Ar as main etching gases. Thereby, tungsten is embedded only in the contact holes 31 and 51, and the tungsten plug 8 is formed. Thereafter, the titanium film 9 was formed to a film thickness of 200 GPa by the sputtering method.
    In the semiconductor device fabricated as described above, that is, the semiconductor device in which the contact hole is formed by the method corresponding to the embodiment of the present invention, the second wiring layer 2 and the third wiring layer 4 and a plurality of tungsten plugs connecting them ( A constant current was sent to the chain (up chain) of TEG comprised of 8), and the voltage which generate | occur | produced in this up chain was measured. This measurement was performed for all one lot of semiconductor devices. The results are shown in the graph of FIG. The higher this voltage measurement, the higher the wiring resistance.
    In addition, only the formation method of the contact holes 31 and 51 was changed as the comparative examples 1 and 2 with respect to the said Example, and all other points produced the semiconductor device of the same structure by the same method.
    In Comparative Example 1, the contact holes 31 and 51 were formed by supplying CF 4 gas, CHF 3 gas, Ar gas, and N 2 gas into the etching chamber during etching of the insulating films 3 and 5, and plasma etching for 250 seconds. . This etching time corresponds to the time when the insulating films 3 and 5 are etched at 19000 Pa. The gas supply amount into the etching chamber is
    Ar; 200 sccm
    CF 4 ; 30 sccm
    CHF 3 ; 30 sccm
    N 2 ; 10 sccm
    It was made. Etching conditions other than that were the same as that of the said Example.
    In Comparative Example 2, the contact holes 31 and 51 were formed by supplying CF 4 gas, CHF 3 gas and Ar gas into the etching chamber during the etching of the insulating films 3 and 5, and plasma etching for 290 seconds. This etching time corresponds to the time when the insulating films 3 and 5 are etched at 23000 Pa. The gas supply amount into the etching chamber is
    Ar; 200 sccm
    CF 4 ; 30 sccm
    CHF 3 ; 30 sccm
    It was made. Etching conditions other than that were the same as that of the said Example.
    Also in Comparative Examples 1 and 2, the voltage generated by sending a constant current to the up chain was measured for all one lot of the manufactured semiconductor device. The result was shown on the graph of FIG. 3 about the comparative example 1, and on the graph of FIG. 4 about the comparative example 2. FIG.
    In Comparative Example 1, as illustrated in FIG. 3, there were 1 to 10 samples each having a voltage measurement value of 0.02 to 0.13 V, and some samples of 0.2 V or more. From this result, if etching for forming the contact holes 31 and 51 is performed only by the plasma etching method in which not only Ar but also N 2 is added to the etching gases CF 4 and CHF 3 , there is a large nonuniformity in wiring resistance within one lot. This could be seen.
    In Comparative Example 2, as shown in FIG. 4, the voltage measurement value was 0.025 V or less in all samples, and the wiring resistance was lower than that of Comparative Example 1, and at the same time, the variation in wiring resistance within one lot was found to be small. However, when the shapes of the contact holes 31 and 51 formed by the method of Comparative Example 2 were examined by SEM (scanning electron microscope), it was found that the diameter was formed larger than the set value.
    On the other hand, in the above-mentioned Example, as shown in FIG. 2, the voltage measurement value became 0.05 V or less in all the samples, and it turned out that wiring resistance is lower than the comparative example 1, and at the same time, the wiring nonuniformity in one lot is small. . Moreover, when the shape of the contact holes 31 and 51 formed by the method of the Example was examined by SEM (scanning electron microscope), it turned out that the diameter is formed in substantially the set value.
    As described above, in this embodiment, as an etching method at the time of forming the contact holes 31 and 51, plasma etching was first performed while supplying Ar and N 2 additionally to the etching gases CF 4 and CHF 3 in the etching chamber. . The processing time of this etching was made into the time in which the thinnest part (part of thickness 10000 GPa) is etched all in the thickness direction from the upper part of the aluminum wiring layer of the insulating films 3 and 5. As shown in FIG. Thereafter, plasma etching was performed without supplying N 2 .
    As a result, the contact hole is prevented from being formed larger than the set value, the wiring resistance of the semiconductor device of the multilayer wiring structure obtained at the same time is suppressed low, and the variation of the wiring resistance in the same lot is also reduced.
    As described above, according to the method of the present invention, AlN formation to the bottom surface of the contact hole is suppressed, retreat of the resist is prevented, and polymer formation to the contact hole sidewall is prevented. As a result, the wiring resistance of the semiconductor device of the multilayer wiring structure can be kept low while preventing the contact hole from being formed larger than the set value, and the variation in the wiring resistance in the same lot can be reduced.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] In the method of forming a contact hole by forming an insulating film on an aluminum wiring layer, using a predetermined etching gas with respect to this insulating film, and dry etching through a resist pattern,
    And after performing the first etching step of etching by adding nitrogen to the etching gas for a predetermined time, the second etching step of etching without adding nitrogen to the etching gas is performed.
    [2" claim-type="Currently amended] The method for forming a contact hole according to claim 1, wherein the processing time of the first etching process is substantially the same time as the time that the minimum film thickness portion of the insulating film is etched in the thickness direction.
    [3" claim-type="Currently amended] The method of claim 1, wherein the etching gas comprises a fluorocarbon gas.
    [4" claim-type="Currently amended] The method for forming a contact hole according to claim 1, wherein the aluminum wiring layer is made of an aluminum alloy containing copper (Cu) and / or silicon (Si).
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    同族专利:
    公开号 | 公开日
    KR100372996B1|2003-02-25|
    TW434816B|2001-05-16|
    WO2000039845A1|2000-07-06|
    US6531067B1|2003-03-11|
    JP3781175B2|2006-05-31|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-12-28|Priority to JP37301298
    1998-12-28|Priority to JP98-373012
    1999-12-28|Application filed by 아사히 가세이 마이크로시스템 가부시끼가이샤
    2001-05-15|Publication of KR20010041383A
    2003-02-25|Application granted
    2003-02-25|Publication of KR100372996B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP37301298|1998-12-28|
    JP98-373012|1998-12-28|
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